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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. unless otherwise noted, this document contains production data. tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 tlv62569 2-a high efficiency synchronous buck converter in sot package 1 1 features 1 ? up to 95% efficiency ? low r ds(on) switches 100 m / 60 m ? 2.5-v to 5.5-v input voltage range ? adjustable output voltage from 0.6 v to v in ? power save mode for light load efficiency ? 100% duty cycle for lowest dropout ? 35- a operating quiescent current ? 1.5-mhz typical switching frequency ? power good output ? over current protection ? internal soft startup ? thermal shutdown protection ? available in sot package ? pin-to-pin compatible with tlv62568 ? create a custom design using the tlv62569 with the webench ? power designer 2 applications ? general purpose pol supply ? set top box ? network video camera ? wireless router ? hard disk driver 3 description the tlv62569 device is a synchronous step-down buck dc-dc converter optimized for high efficiency and compact solution size. the device integrates switches capable of delivering an output current up to 2 a. at medium to heavy loads, the device operates in pulse width modulation (pwm) mode with 1.5-mhz switching frequency. at light load, the device automatically enters power save mode (psm) to maintain high efficiency over the entire load current range. in shutdown, the current consumption is reduced to less than 2 a. the tlv62569 provides an adjustable output voltage via an external resistor divider. an internal soft start circuit limits the inrush current during startup. other features like over current protection, thermal shutdown protection and power good are built-in. the device is available in a sot23 and sot563 package. device information (1) part number package body size (nom) tlv62569 sot23 (5) 2.90 mm 2.80 mm tlv62569p sot23 (6) tlv62569 sot563 (6) 1.60 mm x 1.60 mm tlv62569p sot563 (6) (1) for all available packages, see the orderable addendum at the end of the datasheet. 4 simplified schematic efficiency at 5-v input voltage load (a) efficiency (%) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 60 65 70 75 80 85 90 95 100 d008 v out = 1.2 v v out = 1.8 v v out = 2.5 v v out = 3.3 v r1 200 k r2 100 k sw gnd fb en pg vin c3* c2 10 f r3 499 k c1 4.7 f v in 2.5 v to 5.5 v v pg v out 1.8 v / 2.0 a l1 2.2 h c3: optional tlv62569p copyright 2016, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 simplified schematic ............................................. 1 5 revision history ..................................................... 2 6 device options ....................................................... 3 7 pin configuration and functions ......................... 3 8 specifications ......................................................... 4 8.1 absolute maximum ratings ...................................... 4 8.2 esd ratings .............................................................. 4 8.3 recommended operating conditions ...................... 4 8.4 thermal information .................................................. 4 8.5 electrical characteristics .......................................... 5 8.6 typical characteristics .............................................. 6 9 detailed description .............................................. 7 9.1 overview ................................................................... 7 9.2 functional block diagrams ....................................... 7 9.3 feature description ................................................... 7 9.4 device functional modes .......................................... 8 10 application and implementation .......................... 9 10.1 application information ............................................ 9 10.2 typical application .................................................. 9 11 power supply recommendations ..................... 13 12 layout ................................................................... 14 12.1 layout guidelines ................................................. 14 12.2 layout example .................................................... 14 12.3 thermal considerations ........................................ 14 13 device and documentation support ................. 15 13.1 device support .................................................... 15 13.2 documentation support ....................................... 15 13.3 receiving notification of documentation updates 15 13.4 community resources .......................................... 15 13.5 trademarks ........................................................... 15 13.6 electrostatic discharge caution ............................ 16 13.7 glossary ................................................................ 16 14 mechanical, packaging, and orderable information ........................................................... 16 5 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (december 2016) to revision a page ? added webench ? model ................................................................................................................................................... 1
3 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated (1) for detailed ordering information, please check mechanical, packaging, orderable information at the end of this datasheet. (2) product preview 6 device options part number (1) function package marking package tlv62569dbv - 16af sot23-5 tlv62569pddc (2) power good sot23-6 tlv62569drl (2) - sot563-6 tlv62569pdrl (2) power good sot563-6 7 pin configuration and functions pin functions pin number i/o/pw r description name sot23-5 sot23-6 sot563-6 en 1 1 5 i device enable logic input. logic high enables the device, logic low disables the device and turns it into shutdown. do not leave floating. gnd 2 2 2 pwr ground pin. sw 3 3 4 pwr switch pin connected to the internal fet switches and inductor terminal. connect the inductor of the output filter to this pin. vin 4 4 3 pwr power supply voltage input. pg - 5 6 o power good open drain output pin for tlv62569p. the pull-up resistor should not be connected to any voltage higher than 5.5v. if it's not used, leave the pin floating. fb 5 6 1 i feedback pin for the internal control loop. connect this pin to an external feedback divider. nc - - 6 o no connection pin for tlv62569drl. the pin can be connected to the output or the ground. or leave it floating. pg 1 2 3 6 5 4 en sw gnd vin fb nc/pg 1 2 3 6 5 4 en sw gnd vin fb 1 2 3 5 4 en sw gnd vin fb sot23-5 dbv package (top view) sot23-6 ddc package (top view) sot563-6 drl package (top view)
4 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and the device is not switching. functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) normal switching operation 8 specifications 8.1 absolute maximum ratings over operating temperature range (unless otherwise noted) (1) min max unit voltage (2) vin, en, pg ? 0.3 6 v sw (dc) ? 0.3 v in +0.3 v sw (ac, less than 10ns) (3) ? 3.0 9 v fb ? 0.3 5.5 v operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 8.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 v (1) refer to the application and implementation section for further information. 8.3 recommended operating conditions (1) min typ max unit v in input voltage 2.5 5.5 v v out output voltage 0.6 v in v i out output current 0 2 a t j operating junction temperature ? 40 125 c i sink_pg sink current at pg pin 1 ma (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 8.4 thermal information thermal metric (1) tlv62569 dbv (5 pins) unit r ja junction-to-ambient thermal resistance 188.2 c/w r jc(top) junction-to-case (top) thermal resistance 137.5 c/w r jb junction-to-board thermal resistance 41.2 c/w jt junction-to-top characterization parameter 31.4 c/w jb junction-to-board characterization parameter 40.6 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w
5 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 8.5 electrical characteristics v in = 5.0 v, t j = 25 c, unless otherwise noted parameter test conditions min typ max unit supply i q quiescent current into vin pin not switching 35 ua i sd shutdown current into vin pin en = 0 v 0.1 2 a v uvlo under voltage lock out v in falling 2.3 2.45 v under voltage lock out hysteresis 100 mv t jsd thermal shutdown junction temperature rising 150 c junction temperature falling 130 logic interface v ih high-level input voltage at en pin 2.5 v v in 5.5 v 1.2 0.95 v v il low-level input voltage at en pin 2.5 v v in 5.5 v 0.85 0.4 v t ss soft startup time 800 s v pg power good threshold v fb rising, referenced to v fb nominal 95% v fb falling, referenced to v fb nominal 90% v pg,ol power good low-level output voltage i sink = 1 ma 0.4 v i pg,lkg input leakage current into pg pin v pg = 5.0 v 0.01 a t pg,dly power good delay time v fb falling 40 s output v fb feedback regulation voltage 0.588 0.6 0.612 v r ds(on) high-side fet on resistance 100 m ? low-side fet on resistance 60 i lim high-side fet current limit 3 a f sw switching frequency v out = 2.5 v 1.5 mhz
6 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 8.6 typical characteristics figure 1. quiescent current vs input voltage figure 2. shutdown current vs junction temperature figure 3. fb voltage accuracy junction temperature (c) 6kxwgrzq&xuuhqw $ -40 -10 20 50 80 110 140 0 2 4 6 8 10 12 14 16 18 20 d002 v in = 2.5v v in = 3.6v v in = 5.0v input voltage (v) fb voltage accuracy (%) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 d003 t j = -40c t j = 25c t j = 85c t j = 125c input voltage (v) 4xlhvfhqw&xuuhqw $ 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10 15 20 25 30 35 40 45 50 d001 t j = -40c t j = 25c t j = 85c t j = 125c
7 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 9 detailed description 9.1 overview the tlv62569 is a high-efficiency synchronous step-down converter. the device operates with an adaptive off time with peak current control scheme. the device operates at typically 1.5-mhz frequency pulse width modulation (pwm) at moderate to heavy load currents. based on the v in /v out ratio, a simple circuit sets the required off time for the low-side mosfet. it makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. 9.2 functional block diagrams figure 4. tlv62569 functional block diagram 9.3 feature description 9.3.1 power save mode the device automatically enters power save mode to improve efficiency at light load when the inductor current becomes discontinuous. in power save mode, the converter reduces switching frequency and minimizes current consumption. in power save mode, the output voltage rises slightly above the nominal output voltage. this effect is minimized by increasing the output capacitor. 9.3.2 100% duty cycle low dropout operation the device offers a low input-to-output voltage differential by entering 100% duty cycle mode. in this mode, the high-side mosfet switch is constantly turned on and the low-side mosfet is switched off. the minimum input voltage to maintain output regulation, depending on the load current and output voltage, is calculated as: v in(min) = v out + i out x (r ds(on) + r l ) where ? r ds(on) = high side fet on-resistance ? r l = inductor ohmic resistance (dcr) (1) control logic soft start thermal shutdown uvlo gate drive gnd fb en sw modulator t off gnd zero current detect peak current detect +_ v ref v sw v in + gnd v pg v fb vin pg power good feature is only available in tlv62569p copyright 2016, texas instruments incorporated
8 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated feature description (continued) 9.3.3 soft startup after enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output voltage during a startup time. this avoids excessive inrush current and creates a smooth output voltage rise slope. it also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. the tlv62569 is able to start into a pre-biased output capacitor. the converter starts with the applied bias voltage and ramps the output voltage to its nominal value. 9.3.4 switch current limit the switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail. excessive current might occur with a heavy load or shorted output circuit condition. the tlv62569 adopts the peak current control by sensing the current of the high-side switch. once the high-side switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down the inductor current with an adaptive off-time. 9.3.5 under voltage lockout to avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than v uvlo with v hys_uvlo hysteresis. 9.3.6 thermal shutdown the device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising threshold, t jsd . once the junction temperature falls below the falling threshold, the device returns to normal operation automatically. 9.4 device functional modes 9.4.1 enabling/disabling the device the device is enabled by setting the en input to a logic high. accordingly, a logic low disables the device. if the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. the en input must be terminated and should not be left floating. 9.4.2 power good the tlv62569p has a power good output. the pg pin goes high impedance once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. the pg pin is an open-drain output and is specified to sink up to 1 ma. the power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 v. the pg signal can be used for sequencing of multiple rails by connecting it to the en pin of other converters. leave the pg pin unconnected when not used. table 1. pg pin logic device conditions logic status high z low enable en = high, v fb v pg en = high, v fb v pg shutdown en = low thermal shutdown t j > t jsd uvlo 1.4 v < v in < v uvlo power supply removal v in 1.4 v
9 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference. 10.2 typical application figure 5. tlv62569 1.8-v output application 10.2.1 design requirements for this design example, use the parameters listed in table 2 as the input parameters. table 2. design parameters design parameter example value input voltage 2.5 v to 5.5 v output voltage 1.8 v maximum output current 2.0 a (1) see third-party products disclaimer table 3 lists the components used for the example. table 3. list of components reference description manufacturer (1) c1 4.7 f, ceramic capacitor, 10 v, x7r, size 0805, grm21br71a475ka73l murata c2 10 f, ceramic capacitor, 10 v, x7r, size 0805, grm21br71a106ke51l murata l1 2.2 h, power inductor, size 4mmx4mm, xal4020-222me coilcraft r1,r2,r3 chip resistor,1%,size 0603 std. c3 optional, 6.8 pf if it is needed std. 10.2.2 detailed design procedure 10.2.2.1 custom design with webench ? tools click here to create a custom design using the tlv62569 device with the webench ? power designer. r1 200 k r2 100 k sw gnd fb en pg vin c3* c2 10 f r3 499 k c1 4.7 f v in 2.5 v to 5.5 v v pg v out 1.8 v / 2.0 a l1 2.2 h c3: optional tlv62569p copyright 2016, texas instruments incorporated
10 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated (1) inductor tolerance and current de-rating is anticipated. the effective inductance can vary by +20% and -30%. (2) capacitance tolerance and bias voltage de-rating is anticipated. the effective capacitance can vary by +20% and -50%. (3) this lc combination is the standard value and recommended for most applications. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 10.2.2.2 setting the output voltage an external resistor divider is used to set output voltage according to equation 2 . when sizing r2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of 200 k for r2. larger currents through r2 improve noise sensitivity and output voltage accuracy but increase current consumption. (2) a feed forward capacitor, c3 improves the loop bandwidth to make a fast transient response (shown in figure 19 ). 6.8-pf capacitance is recommended for r2 of 100-k resistance. a more detailed discussion on the optimization for stability vs. transient response can be found in slva289 . 10.2.2.3 output filter design the inductor and output capacitor together provide a low-pass filter. to simplify this process, table 4 outlines possible inductor and capacitor value combinations. checked cells represent combinations that are proven for stability by simulation and lab test. further combinations should be checked for each individual application. table 4. matrix of output capacitor and inductor combinations v out [v] l [ h] (1) c out [ f] (2) 4.7 10 22 2 x 22 100 0.6 v out < 1.2 1 + 2.2 ++ (3) 1.2 v out < 1.8 1 + + 2.2 ++ (3) + 1.8 v out 1 + + + 2.2 ++ (3) + + ? ? ? ? + = ? ? ? ? + = 2 1 1 6.0 2 1 1 r r v r r v v fb out
11 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 10.2.2.4 inductor selection the main parameters for inductor selection is inductor value and then saturation current of the inductor. to calculate the maximum inductor current under static load conditions, equation 3 is given: where: ? i out,max is the maximum output current ? i l is the inductor current ripple ? f sw is the switching frequency ? l is the inductor value (3) it is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than i l,max . in addition, dc resistance and size should also be taken into account when selecting an appropriate inductor. 10.2.2.5 input and output capacitor selection the architecture of the tlv62569 allows use of tiny ceramic-type output capacitors with low equivalent series resistance (esr). these capacitors provide low output voltage ripple and are thus recommended. to keep its resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is recommended to use x7r or x5r dielectric. the input capacitor is the low impedance energy source for the converter that helps provide stable operation. a low esr multilayer ceramic capacitor is recommended for best filtering. for most applications, 4.7- f input capacitance is sufficient; a larger value reduces input voltage ripple. the tlv62569 is designed to operate with an output capacitor of 10 f to 47 f, as outlined in table 4 . 10.2.3 application performance curves v in = 5 v, v out = 1.8 v, l = 2.2 h, t a = 25 c, unless otherwise noted. figure 6. 1.2-v output efficiency figure 7. 1.8-v output efficiency load (a) efficiency (%) 60 65 70 75 80 85 90 95 100 1m 10m 100m 1 2 d004 v in = 2.5 v v in = 3.3 v v in = 5.0 v load (a) efficiency (%) 60 65 70 75 80 85 90 95 100 1m 10m 100m 1 2 d005 v in = 2.5 v v in = 3.3 v v in = 5.0 v sw in out out l l max , out max ,l f l v v 1 v i 2 i i i - = d d + =
12 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated figure 8. 2.5-v output efficiency figure 9. 3.3-v output efficiency v in = 5 v figure 10. load regulation v out = 1.8 v figure 11. line regulation v in = 5 v figure 12. switching frequency vs load i out = 1 a figure 13. switching frequency vs input voltage load (a) efficiency (%) 60 65 70 75 80 85 90 95 100 1m 10m 100m 1 2 d007 v in = 5.0 v load (a) switching frequency (khz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 500 1000 1500 2000 2500 d011 v out = 1.2 v v out = 1.8 v v out = 2.5 v v out = 3.3 v input voltage (v) switching frequency (khz) 2.5 3 3.5 4 4.5 5 5.5 0 500 1000 1500 2000 2500 d012 v out = 1.2 v v out = 1.8 v v out = 2.5 v v out = 3.3 v load (a) load regulation (%) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -1 -0.5 0 0.5 1 1.5 2 2.5 3 d009 v out = 1.8 v v out = 3.3 v input voltage (v) line regulation (%) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1.0 -0.5 0.0 0.5 1.0 d010 i out = 0.5a i out = 1.0a i out = 2.0a load (a) efficiency (%) 60 65 70 75 80 85 90 95 100 1m 10m 100m 1 2 d006 v in = 3.3 v v in = 5.0 v
13 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated i out = 1 a figure 14. pwm operation i out = 0.1 a figure 15. power save mode operation i out = 2 a figure 16. startup and shutdown with load i out = 0.1 a figure 17. startup and shutdown with load load step 0.8 a to 2 a, 1a/ s slew rate figure 18. load transient load step 0.8 a to 2 a, 1a/ s slew rate c3 = 6.8 pf figure 19. load transient 11 power supply recommendations the power supply to the tlv62569 must have a current rating according to the supply voltage, output voltage and output current. 7lph v',9 d017 v out 0.2v/div i coil 1a/div 7lph v',9 d018 v out 0.2v/div i coil 1a/div 7lph v',9 d015 v en 3v/div v out 1v/div i coil 2a/div 7lph v',9 d016 v en 3v/div v out 1v/div i coil 0.5a/div time - 500ns/div d013 v sw 2v/div v out 10mv/div ac i coil 0.5a/div 7lph v',9 d014 v sw 2v/div v out 0.1v/div ac i coil 0.5a/div
14 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 12 layout 12.1 layout guidelines the pcb layout is an important step to maintain the high performance of the tlv62569 device. ? the input/output capacitors and the inductor should be placed as close as possible to the ic. this keeps the power traces short. routing these power traces direct and wide results in low trace resistance and low parasitic inductance. ? the low side of the input and output capacitors must be connected properly to the power gnd to avoid a gnd potential shift. ? the sense traces connected to fb are signal traces. special care should be taken to avoid noise being induced. keep these traces away from sw nodes. ? gnd layers might be used for shielding. 12.2 layout example figure 20. tlv62569 layout 12.3 thermal considerations implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. many system-dependent issues such as thermal coupling, airflow, convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. two basic approaches for enhancing thermal performance are listed below: ? improving the power dissipation capability of the pcb design ? introducing airflow in the system for more details on how to use the thermal parameters, see the application notes: thermal characteristics application notes szza017 and spra953 . pac101 pac601 par201 par202 par201 vin fb sw gnd en vin vout gnd c2 l1 c1 r1 r2
15 tlv62569 , tlv62569p www.ti.com slvsdg1a ? december 2016 ? revised march 2017 product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 13 device and documentation support 13.1 device support 13.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 13.1.2 development support 13.1.2.1 custom design with webench ? tools click here to create a custom design using the tlv62569 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 13.2 documentation support 13.2.1 related documentation semiconductor and ic package thermal metrics application report ( spra953 ) thermal characteristics of linear and logic packages using jedec pcb designs application report ( szza017 ) 13.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.5 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments.
16 tlv62569 , tlv62569p slvsdg1a ? december 2016 ? revised march 2017 www.ti.com product folder links: tlv62569 tlv62569p submit documentation feedback copyright ? 2016 ? 2017, texas instruments incorporated 13.5 trademarks (continued) all other trademarks are the property of their respective owners. 13.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 13.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 12-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TLV62569DBVR active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 16af tlv62569dbvt active sot-23 dbv 5 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 16af xlv62569pddcr active sot-23-thin ddc 6 3000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 12-apr-2017 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TLV62569DBVR sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv62569dbvt sot-23 dbv 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 package materials information www.ti.com 24-mar-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TLV62569DBVR sot-23 dbv 5 3000 210.0 185.0 35.0 tlv62569dbvt sot-23 dbv 5 250 210.0 185.0 35.0 package materials information www.ti.com 24-mar-2017 pack materials-page 2

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